This invention relates generally to a method for making bipolar transistors. More particularly, the invention relates to a method of making complementary vertical bipolar junction transistors fabricated in silicon on a sapphire substrate.
Many semiconductor electronic devices are fabricated on a bulk, crystalline, silicon substrate. Yet, for a number of specific devices and applications, a better choice of substrate material is sapphire. In such cases, a thin layer of silicon is deposited on an insulating sapphire base. This combination has become known as silicon-on-sapphire, and is a specific example of what is known as silicon-on-insulator technology.
Bipolar junction transistors fabricated of silicon-on-sapphire technology have several important advantages when compared to transistors fabricated on bulk silicon. Total isolation between transistors is possible by removing any silicon surrounding the transistors down to the sapphire level. This produces an island that inhibits cross-talk between closely located devices and improves chip reliability when packing density is high.
It is known that bipolar transistors experience problems associated with parasitic capacitance. The severity of this capacitance increases as transistors are made smaller. Because of the insulating qualities of the sapphire substrate, relatively little capacitance between a transistor""s collector and the sapphire will exist. In addition, all interconnecting lines can be located on the sapphire substrate, thereby contributing little to parasitic capacitance. This allows high-frequency components to be located relatively near one another on the same chip, with the benefit of unwanted feedback being eliminated or substantially reduced. Thus the speed and reliability of transistors fabricated of silicon-on-sapphire is typically enhanced.
It is also known that silicon-on-sapphire devices are more radiation hardened than those fabricated on bulk silicon. Such radiation hardness permits devices to operate more effectively in environments containing high levels of ionizing radiation.
While the attributes of fabricating bipolar junction transistors of silicon-on-sapphire are well known, such fabrication has been accomplished with varying degrees of success. An early approach to fabricating this type of transistor based on silicon epitaxial growth on a sapphire substrate can be found in U.S. Pat. No. 4,050,965. This patent describes a process for fabricating bipolar junction transistors integrated with CMOS devices formed laterally on the L same integrated circuit. Other early examples of methods for making bipolar transistors of silicon-on-sapphire can be found in U.S. Pat. No. 3,943,555 which discloses the use of ion implantation to produce a planar bipolar junction transistor that is isolated on a substrate. U.S. Pat. No. 3,974,560 discloses the use of ion implantation and diffusion to fabricate a lateral bipolar transistor.
More recent methods for fabricating a lateral bipolar junction transistor can be found in U.S. Pat. No. 5,298,786, which describes the use of polysilicon in the fabrication of a transistor having an edge-strapped base contact. U.S. Pat. No. 5,198,375 discloses the use of a dielectric layer to form both vertical and lateral transistor devices. U.S. Pat. No. 5,374,567 describes a method of fabricating a low leakage current bipolar junction transistor on silicon-on-sapphire for use in operational amplifiers utilizing all-implant technology, improved silicon conditioning and low temperature annealing. In U.S. Pat. No. 5,714,793, an intricate process is used to fabricate true complementary vertical bipolar junction transistors of silicon-on-sapphire.
Most of the development of bipolar junction transistors of silicon-on-sapphire has been concentrated in the area of lateral bipolar junction transistors, epitaxial vertical bipolar junction transistors, and heteroepitaxy bipolar junction transistors. This work has been recorded respectively by P. K. Vasudev in his article in the IEEE Circuits and Devices magazine titled: Recent Advances in Solid-Phase Epitaxial Recrystallization of SOS with Applications to CMOS and Bipolar Devices, of July 1987, pp. 17-19: by F. P. Heiman and P. H. Robinson in their article in Solid State Electronics titled: Silicon-on-Sapphire Epitaxial Bipolar Transistors of 1968, Volume 11, pp. 411-418; and by E. N. Cartagena, B. W. Offord and G. Garcia in their article in Electronics Letters titled: Bipolar Junction Transistors Fabricated in Silicon-on-Sapphire of 1992, Volume 28, pp. 983-985.
Traditional bipolar circuitry relies on high performance vertical devices for many of the circuit dynamic functions, while lateral devices provide the biasing and loading functions of the circuit. Experience has shown that lateral devices provide poor circuit element performance, such as low current gain, inadequate current carrying capability and low frequency response. In addition, lateral bipolar transistors occupy a relatively large area of a substrate and typically have high parasitic capacitance. In many applications, limitations of a circuit are determined by the poor performance of the lateral devices. As a consequence, vertical bipolar transistors are commonly chosen for use in high performance/high speed integrated circuits.
Complementary bipolar circuits with high performance vertical devices in the signal path offer enhanced capability of push-pull circuits for both analog and digital applications. Complementary bipolar circuits can also reduce power dissipation, increase switching speed and improve the flexibility of the overall circuit design.
Specific benefits gained by fabricating complementary bipolar circuits of silicon-on-sapphire technology include latch-up immunity, the ability to achieve high packing density, radiation hardness and the capability of operating circuits at a higher frequency response.
In a typical silicon-on-sapphire device, the thickness of the epitaxial layer of silicon on the sapphire base is between 0.5 and 5 micrometers (xcexcm). The quality of this silicon epitaxial layer will play a direct role in the success of the silicon-on-sapphire device. Poor quality silicon will prevent the fabrication of a satisfactory bipolar junction transistor when diffusion of impurities into the silicon layer is required.
The silicon layer on a sapphire substrate will generally lack good crystal structure when compared to bulk silicon. In addition, a relatively higher density of defects in the epitaxial silicon will be found when compared to bulk silicon. A problem associated with the larger defect density is low minority carrier lifetime. Lifetimes that range from as low as 0.1 ns to 10 ns are typical for these epitaxial layers, compared to minority carrier lifetimes of 100 ns to 1 microsecond or more for bulk silicon. Since a bipolar junction transistor is a minority carrier device, efficient operation requires a relatively high minority carrier lifetime in the base region.
To improve the quality of a silicon epitaxial layer on a sapphire base, recrystallization techniques have been used. One such process, known as the double solid phase epitaxy technique, has been described by P. K. Vasudev in his 1987 article in IEEE Circuits and Devices noted above.
While recrystallization techniques improve the quality of the silicon epitaxial layer, further improvements are required to make bipolar junction transistors more practical for many semiconductor circuit applications. Such practicality could be advanced by a process of fabricating complimentary vertical bipolar junction transistors having fewer steps than those required for true complementary vertical bipolar junction transistors.
The invention is a method for fabricating complementary vertical bipolar junction transistors of silicon-on-sapphire in fewer steps than required for true complimentary vertical bipolar junction transistors. Initially a thin layer of silicon is grown on a sapphire substrate. The silicon layer is improved using double solid phase epitaxy. The silicon is then patterned and implanted with P+-type and N+-type dopants. Subsequently a micrometer scale N-type layer is grown that acts as both the intrinsic base for an PNP transistor and as the collector for an NPN transistor. The intrinsic base for the NPN is then formed, followed by the emitter, collector and ohmic contact regions being selectively masked and implanted. Conductive metal is then formed between protecting oxide to complete the complementary vertical bipolar junction transistors.
An object of the invention is to provide an improved method for fabricating vertical bipolar junction transistors.
Another object of the invention is to provide an improved method for fabricating vertical bipolar junction transistors.
Yet another object of the invention is to provide an improved method for fabricating complementary vertical bipolar junction transistors.
Yet still another object of the invention is to provide a simplified method for fabricating complementary vertical bipolar junction transistors.
Still another object of the invention is to provide an improved method for fabricating complementary vertical bipolar junction transistors of silicon-on-sapphire.
Still a further object of the invention is to provide an improved method for fabricating complementary vertical bipolar junction transistors of silicon-on-sapphire utilizing wide base PNP transistors.
Other objects, advantages and new features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanied drawings.